CMP Slurry
Chemical Mechanical Polishing (CMP) planarizes silicon wafers or other substrate materials during processing using chemical etching and mechanical force. Integrated circuits generally adopt multi‑layer three‑dimensional wiring, requiring repeated cycles in front‑end manufacturing. CMP is a key process for wafer planarization and an important step in advancing process technology nodes.
- • Logic Chips: 28nm and below processes
- • Memory Chips: 1X-2Xnm technology nodes
- • Specialty Processes: Applicable to all technology nodes
- • 8/12-inch processes
- • The Poly-Si removal rate is tunable, covering a wide range of process requirements from low to high polishing rates, and supports customized development.
- • Features a high selectivity ratio for Ox & SiN, excellent auto-stop capability, and superior dishing control.
- • Boasts a wide process window with stable performance over a broad temperature range. The dilution ratio can be adjusted for different applications to flexibly meet process requirements.
- • Logic Chips/Memory Chips: Applicable to all technology nodes
- • 8/12-inch processes
- • High dilution ratio design delivers distinct economic advantages and helps optimize inventory management.
- • Wide application scope, with performance fully comparable to mainstream competitors; customizable adjustments available for different processes.
- • Favorable process window reduces yield loss caused by parameter fluctuations, ensuring stable and reliable performance.
- • 14nm and below processes
- • 12-inch processes
- • Provides broad and linear selectivity tuning capability, supporting customizable requirements from equal ratio to high selectivity, suitable for various processes such as shallow trench isolation, contact holes, and metal gates.
- • Achieves ultra-high SiN:Oxide selectivity while controlling SiN dishing effectively.
- • Delivers stable removal rate and selectivity, excellent within-wafer and wafer-to-wafer uniformity, enabling high-level surface planarity.
- • Memory Chips: W CMP (12-inch)
- • Logic Chips: 8-inch/12-inch W CMP
- • Features tunable W-to-Ox selectivity with excellent dishing control.
- • Provides good uniformity and planarization capability, as well as accurate EPD detection.
- • Delivers excellent defect performance with adjustable surface roughness; optimized formulation further enhances product performance.
- • 8/12-inch process, dielectric material (SiO₂) removal and planarization
- • Wafer thinning process
- • Ceria-based slurry
- • High oxide removal rate with outstanding planarization performance.
- • High dilution ratio design delivers excellent cost efficiency and inventory management benefits.
- • Wide process adjustable range, adapting to requirements of different integration structures and equipment environments.
- • 8/12-inch process, dielectric material (SiO₂) removal and planarization
- • Wafer thinning process
- • Silica-based slurry
- • Provides industry-leading material removal rate, significantly improving production efficiency and reducing costs. Featuring exceptional global and local planarization capabilities, it fully meets the stringent nanometer-level flatness requirements of advanced processes.
- • Wide process window, insensitive to variations in pressure, rotation speed, flow rate and other parameters, ensuring high yield and stability in mass production.
- • Product portfolio covers acidic to alkaline systems, precisely matching different underlying materials (e.g., STI, ILD, PMD) and equipment environments. Customized optimization is available for customers’ specific processes, such as post-CMP cleaning compatibility for copper, tungsten and poly-Si.
- • Formulated in line with green chemistry principles, committed to reducing the use of hazardous chemicals and lowering wastewater treatment burdens.
